The technology disclosed therein relates to built-in-self-testing of memory elements of circuits wherein flexibility in the selection of test algorithms applied during a BIST is enhanced and also to circuits containing components for performing such BIST operations.
In one known approach for performing a BIST of a memory, prior to performance of the BIST, a set of algorithms for use in BIST testing are specified. A memory BIST (MBIST) testing tool will create or configure an MBIST controller to perform the specified set of algorithms. The entire set of algorithms being run during the BIST. With this approach, the time required for a BIST test may be unnecessarily increased because algorithms are being run that are not needed to achieve desired test coverage.
It is known in built-in-self-test (BIST) hardware configured for testing memories to perform setup steps during the last step of a given algorithm prior to launching the next algorithm in the series. For example, the next addressing scheme for performance of the next algorithm may be setup at this time. Also, each test or algorithm can be applied to each memory concurrently or sequentially. A sequential interleaved approach is also known where, for example, data is written simultaneously to all memories with one retention test.
It is also known to perform diagnostics testing using one or two registers to store error information. In known approaches, a BIST is run at a BIST clock rate. If an error, e.g., error “x”, is detected, it is loaded at the BIST clock rate into an error register along with the address of the error. The error may be unloaded to off-chip automatic test equipment (ATE) or a tester at an ATE clock rate that is much slower than the BIST clock rate. If the error register has not been cleared of the error information when the next error (error “x+1”) is detected, the BIST halts. Following the loading of the “error x+1” information, the BIST returns to the start of the first algorithm of the entire set of algorithms of the BIST and restarts. When the location of the error “x+1” is again reached, this error is ignored and testing continues. Previously detected and processed error information (e.g., error “1” through error “x”) are also ignored. In some systems a second error register is provided for storage of the error associated information. If a subsequent error (e.g., error “x+2”) is detected before space is available in a register for storing the “error x+2” information, the BIST is stopped to allow error register space to be cleared for storage of the subsequent error information. Again, the BIST restarts at the beginning of the first algorithm of the entire set of algorithms of the BIST with the BIST ignoring errors that were previously detected. This increases the time required to perform diagnostics as previously satisfactory algorithms are rerun in many cases to get beyond the algorithms including steps where errors were detected.
Therefore, a need exists for built-in-self-test memory approaches that increase the speed of memory BIST operations.